INT J COMPUT COMMUN, Vol 3, No 2
Professor Angel Vassilev Nikolov, National University of Lesotho
Abstract
We develop an analytical model of multiprocessor with private caches and shared memory and obtain the following results: the instantaneous state probabilities and the steady-state probabilities of the system. Both transient behaviour and equilibrium can be studied and analyzed. We showed that results can be applied to determine the output parameters for both blocking and non-blocking caches.
Introduction
Shared memory multiprocessors are widely used as platforms for technical and commercial computing. Performance evaluation is a key technology for design in computer architecture. The continuous growth in complexity of systems is making this task increasingly complex. In general, the problem
of developing effective performance evaluation techniques can be stated as finding the best trade-off between accuracy and speed.
The most common approach to estimate the performance of a superscalar multiprocessor is through building a software model and simulating the execution of a set of benchmarks. Since processors are synchronous machines, however, simulators usually work at cycle-level and this leads to enormous slowdown. It might take hours even days to simulate. For memory structures relatively accurate analytical models were developed through
extensive use of various queuing systems. Open queue system with Poisson arrivals and exponential service times is considered quite good for description of memory hierarchies. Our focus is on the impact of the cache-coherence protocols on the overall system performance.
The most commonly used technique for this purpose is the Mean Value Analysis (MVA). It allows the total number of the customers to be fixed (closed queue system), and this seems to be more adequate representation of the processes of self-blocking requestors. Calculations of output parameters such as residency times, waiting times and utilization are shown in. MVA is based on the forced flow that means in equilibrium output rate equals input rate. However, instantaneously, we can have input rate different from output rate, so that the instantaneous probabilities could be different from equilibrium. MVA
offers no possibility to study transient effects.
Moreover, the assumption of exponential service times is not realistic, in fact all bus access times and memory access times are constants. It will be seen later in this paper that state probabilities depend on the server’s time density function.
We use the technique of Markov processes to describe the behaviour of the multiprocessor implementing cache-coherence protocols