K. O. Setetemela I Department of Mathematics and Computer Science I National University of Lesotho
Internet of things (IoT) technology is making it possible for a wide variety of end-user devices to be connected to the internet, leading to richness and accuracy of real data that would previously have needed much more cumbersome and expensive methods. But this connectedness also leads to more challenges in data security and the increased risk of cyber-attacks. Improved, and faster, security schemes have become a key requirement of these loT technologies. Field Programmable Gate Arrays (FPGAs) have been used to accelerate various cyber-security algorithms. However, while FPGAs are capable of massive computational power, through their highly parallel nature, they are generally difficult to program; and considering the design of modern encryption schemes this is posing a significant bottleneck to progress in security for these architectures. This paper investigates the use of a Python-based high-level FPGA design tool-flow for rapid prototyping of loT cryptosystems. In this paper we implement a version of the Advanced Encryption Standard (AES) algorithm, with block and key sizes of 128bits, using the Python-based tool-flow. The design is functionally verified, a Verilog hardware implementation is generated, simulated and then executed on an FPGA platform. The performance of the resulting FPGA design is analyzed in terms of resource utilization and throughput, and is compared against similar hand-written AES implementations reported in the literature. We found our FPGA implementation had a frequency of 512.742 MHz and a throughput of 65.63Gbps which is more than fast enough for most IoT applications.